The present invention generally relates to a method and an apparatus for processing floating point data which are used in the central processing units of digital computers, and which are adapted to effect the four fundamental arithmetic computations of floating point data, and more particularly, the four fundamental arithmetic computations of floating point data and rounding and normalizing computations in accordance with ANSI/IEEE Standard for Binary Floating Point Arithmetic P754.
The conventional floating point data adding apparatus is shown in the block diagram of FIG. 24. An addition operation is effected with respect to the mantissa data upon the subtraction of different signs or upon the addition of the same signs of two floating point data numbers. A subtraction operation is effected with respect to the mantissa data upon the addition of different signs or upon the subtraction of the same signs of two floating point data numbers. The mantissa addition or subtraction operation is determined beforehand according to the signs of the input data and according to input instructions.
Referring still to FIG. 24, reference numeral 151 denotes a register for storing the mantissa of one of two floating point data numbers having an exponent which is not smaller than the exponent of the other of the two floating-point data numbers. Reference numeral 152 denotes a resister for storing the mantissa of the other of the two floating-point data aligned to the exponent of the one of the two floating point data. Reference numeral 153 denotes a complementer which takes the 1`s complement of the output of the register 152 at the time of a subtraction operation. Reference numeral 154 denotes an adder which receives outputs of the register 151 and the complementer 153 and which executes the addition operation with the carry input (Cin) into the least significant bit being 0, and executes the substraction operation with the carry input (Cin) being 1. Reference numeral 155 denotes a register for accommodating the output of the adder 154. Reference numeral 156 denotes a shift number generating circuit for generating shift numbers for normalization of the output of the adder 154. Reference numeral 157 denotes a barrel shifter which is adapted to effect a bit shift according to a bit number output by the shift number generating circuit 156 with respect to the output of the register 155 for realizing the normalization. Reference numeral 158 denotes a register for accommodating the output of the barrel shifter 157. Reference numeral 159 denotes a round value generating circuit which is adapted to control the round addition in accordance with the value retained in the register 158, the round mode and the round precision. That is, the round value generating circuit generates a round addition value in which the least significant bit (L) corresponding to the round precision is 1 and the remaining bits are 0 when rounding up, and generates a round addition value in which all the bits are 0 when rounding down. Reference numeral 160 denotes an adder for adding the output of the register 158 and the output of the round value generating circuit 159. Reference numeral 161 denotes an R1 shifter for shifting by 1 bit the output of the adder 160 in the least significant bit direction (hereinafter referred to as rightward). Reference numeral 162 denotes a register for accommodating the mantissa of the addition or subtraction result to be obtained by the output of the R1 shifter 161.
The operation of the above-described conventional floating point data addition and subtraction will be described herebelow.
First, a case where the augend (or minuend) and the addend (or subtrahend) are the basic single precision format according to ANSI/IEEE Standard for Binary Floating-Point Arithmetic P754 (hereinafter referred to as single precision), and where the sum or difference is also rounded in single precision, will be described.
(1) Pre-Processing Start Step
The mantissa of the one of the augend (or minuend) and the addend (or subtrahend) which has an exponent which is not smaller than the exponent of the other of the augend (or minuend) and the addend (or subtrahend) is accommodated in the register 151. The mantissa of the other of the augend (or minuend) and the addend (or subtrahend) is aligned to the exponent of the mantissa stored in the register 151 and is accommodated in the register 152. The bits which have been dropped off upon the alignment are accommodated, in the register 152, collectively as a round bit (R) having the weight of 2.sup.-24 which is one bit position lower than the least significant bit (L) and a sticky bit (S) which is the logical OR of the bits of the aligned mantissa having the weight of 2.sup.-25 or lower.
(2) Step 1
The complementer 153 and the adder 154 add (or subtract) the two mantissas retained in the register 151 and the register 152 so as to accommodate the result in the register 155. Upon adding, the complementer 153 outputs into the adder 154 the output of the register 152 as is and the Cin of the adder 154 is 0. Upon subtraction, the complementer 153 applies the 1's complement of the output of the register 152 to the adder 154 and the Cin of the adder 154 is 1.
(3) Step 2
The shift number generating circuit 1546 generates the shift number for normalization of the output of the adder 154. The barrel shifter 157 effects the shifting of the output of the register 155 in accordance with the output of the shift number generating circuit 156 so as to effect the normalization shifting operation with respect to the computation result of the step 1. At this time, the barrel shifter 157 generates the shift results down to the least significant bit (L), the round it (R) having the weight of the 2.sup.-24 lower by one unit of the least significant bit, a sticky bit (S) which is the logical OR of the bits having the weight of 2.sup.-25 or lower and accommodates them in the register 158.
(4) Step 3
The round value generating circuit 159 generates the round addition value in accordance with the least significant bit (L) retained in the register 158, the round bit (R), the sticky bit (S), the round mode, the round precision and the sign of the operation result. The generated round addition value has a value in which the bit having the weight of 2.sup.-23 is 1 and the remaining bits are 0 when the round addition signal is 1, and a value in which all the bits are 0 when the round addition signal is 0, in accordance with the input, output relation chart shown in FIG. 11. RM, RP, RN, RZ denote in order the directed rounding toward the nearest even mode stipulated in the ANSI/IEEE Standard for Binary Floating-Point Arithmetic P754. The adder 160 adds the output of the register 158 and the output of the round value generating circuit 159. The R1 shifter 161 shifts, by one bit rightward, the output of the adder 160 when overflow has been generated in the adder 160, and otherwise accommodates the output of the adder 160 as is in the register 162 so as to complete the processing.
A case where the augend (or minuend) and the addend (or subtrahend) are the basic double precision format according to ANSI/IEEE Standard for Binary Floating-Point Arithmetic P754 (hereinafter referred to simply as double precision), and where the sum or difference is also rounded in double precision, will be described.
(1) Pre-Processing Start Step
The mantissa of the one of the augend (or minuend) and the addend (or subtrahend) which has an exponent which is not smaller than the exponent of the other of the augend (or minuend) and the addend (or subtrahend) is accommodated in the register 151. The mantissa of the other of the augend (or minuend) and the addend (or subtrahend) is aligned to the exponent of the mantissa stored in the register 151 and is accommodated in the register 152. The bits which have been dropped off upon the alignment are accommodated in the register 152 collectively as a round bit (R) having the weight of 2.sup.-53 which is one bit position lower than the least significant bit (L) and a sticky bit (S) which is the logical OR of the bits of the aligned mantissa having the weight of 2.sup.-54 or lower.
(2) Step 1
The complementer 153 and the adder 154 add (or subtract) the two mantissas retained in the register 151 and the register 152 so as to accommodate the result in the register 155. For adding, the complementer 153 outputs into the adder 154 the output of the register 152 as is and the Cin of the adder 154 is 0. For subtracting, the complementer 153 applies the 1's complement of the output of the register 152 to the adder 154 and the Cin of the adder 154 is 1.
(3) Step 2
The shift number generating circuit 156 generates the shift number for normalization of the output of the adder 154. The barrel shift 157 effects the shifting of the output of the register 155 in accordance with the output of the shift number generating circuit 156 so as to effect the normalization shifting operation with respect to the operation result of the step 1. At this time, the barrel shifter 157 generates the shift results down to the least significant bit (L), the round bit (R) having the weight of the 2.sup.-53 lower by one unit of the least significant bit, a sticky bit (S) which is the logical OR of the bits having the weight of 2.sup.-54 or lower and accommodates them in the register 158.
(4) Step 3
The round value generating circuit 159 generates the round addition value in accordance with the least significant bit (L) retained in the register 158, the round bit (R), the sticky bit (S), the round mode, the round precision and the sign of the operation result. The generated round addition value a value in which a bit having the weight of 2.sup.-52 1 is and the remaining bits are 0 when the round addition signal is 1, and a value in which all the bits are 0 when the round addition signal is 0, in accordance with the input, output relation chart shown in FIG. 11. The adder 160 adds the output of the register 158 and the output of the round value generating circuit 159. The R1 shifter 161 shifts by one bit rightward the output of the adder 160 when overflow has been generated in the adder, and otherwise accommodates the output of the adder 160 as is in the register 162 so as to complete the processing.
The conventional floating point data multiplication apparatus is shown in the block diagram of FIG. 25.
In FIG. 25, reference numeral 251 denotes a multiplicand register for retaining the multiplicand which consists of a 1 bit signal portion 251s, an 11 bit exponent portion 251e, and a 53 bit mantissa portion 251f. Reference numeral 252 denotes a multiplier register for retaining the multiplier which consists of a 1 bit sign portion 251s, an 11 bit exponent portion 252e, and a 53 bit mantissa portion 252f. The most significant bit of the multiplicand register mantissa portion 251f and the multiplier register mantissa portion 252f is a so-called "hidden bit" having the weight of 2.sup.0 and is 1 in the normalized number. Except for this bit, the multiplicand register 251 and the multiplier register 252 both conform to the double precision format. Reference numeral 253 denotes a sign generating circuit for reading the signs of the multiplicand and multiplier from the multiplicand register sign portion 251s and the multiplier register sign portion 252s so as to generate the sign of the produce. Reference numeral 254 denotes an exponent adder of 11 bits for reading the exponents of the multiplicand and the multiplier from the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e so as to compute the exponent of the product. Reference numerals 255 and 256 denote selectors of 11 bits for respectively selecting the two inputs of the exponent adder 254. Reference numeral 257 denotes a latch of 11 bits for retaining the output of the exponent adder 254 to be input into the exponent adder 254 again through the selector 255. Reference numeral 258 denotes a bias correction value generating circuit for generating the bias (deviation) of 11 bits in a step of computing the exponent of the product. Reference numeral 259 denotes a normalized correction value generating circuit for generating a constant for increasing by 1 the exponent through the normalization of a 1 bit shift of the mantissa of the product. Reference numeral 260 denotes a multiplicand upper, lower selecting circuit for reading the multiplicand register mantissa portion 251f, and selecting and outputting the upper 27 bits or the lower 27 bits (the most significant bit at this time is 0). Reference numeral 261 denotes a multiplier upper, lower selecting circuit for reading the multiplier resister mantissa portion 252f, and selecting and outputting the upper 27 bits or the lower 27 bits (the most significant bit at this time is 0). Reference numeral 262 denotes a multiplying unit for multiplying the output of the multiplicand upper, lower selecting circuit 260 of 27 bits by the output of the multiplier upper, lower selecting circuit 261 of 27 bits so as to respectively output the sum of 54 bits and the carry of 54 bits. Reference numerals 263 and 264 denote latches of 54 bits for retaining the sum output and the carry output of the multiplying unit 262. Reference numeral 265 denotes a product generating adder of 54 bits for adding the sum output and carry output of the multiplying unit 262 retained in the latch 263 and the latch 264. Reference numeral 266 denotes a latch of 54 bits for retaining the output of the product generating adder 265. Reference numeral 267 denotes a round adding value generating circuit for generating the constant in the adding operation for rounding the mantissa of the product into the single precision or the double precision. Reference numeral 268 denotes a selector of 54 bits for selecting the output of the round addition value generating circuit 267 or the value of the latch 266. Reference numeral 269 denotes a mantissa adder of 54 bits for adding the output of the selector 268 and the value to be retained in the latch 273 to be described later. Reference numeral 270 denotes a logical OR gate for computing the logical OR of the overflow from the most significant bit of the product generating adder 265 and the overflow from the most significant bit of the mantissa adder 269. Reference numeral 271 denotes a shifter of 54 bits for shifting by 0 bits, 1 bit or 26 bits the output of the mantissa adder 269 in the least significant bit direction. Reference numeral 272 denotes a sticky bit generating circuit for inputting the lower 30 bits of the output of the mantissa adder 269 and the shift overflow from the least significant bit of the 26 bits in the shifter 271 so as to generate the sticky bit in accordance with the single precision rounding or double precision rounding. Reference numeral 273 denotes a latch of 54 bits for retaining the output of the shifter 271. Reference numeral 274 is a product register for retaining the product which consists of a 1 bit sign portion 274s, an 11 bit exponent portion 274e, and a 53 bit mantissa portion 274f. The most significant bit of the product register mantissa portion 274f is also a so-called "hidden bit" having the weight of 2.sup.0 and is 1 in the normalized number. Except for this bit, the product register 274 conforms to the double precision format.
FIG. 26 is a performance illustrating chart showing the constant generated by the round addition value generating circuit 267 shown in FIG. 25. A round addition value D is generated in which only the 24th bit from the most significant bit is 1 and the remaining bits are 0, and a round addition value E is generated in which only the 2nd bit from the least significant bit is 1 and the remaining bits are 0.
The operation of the conventional floating point data multiplying apparatus will be described hereinafter.
First, a case where the multiplicand and the multiplier are the single precision, and where the product is also round in the single precision, will be described hereinafter with the use of the operation flow chart of the single precision multiplication shown in FIG. 27. FIG. 27 shows the contents of the operation of each of the processing steps of the exponent adder 254, the multiplying unit 262, the product generating adder 265, the mantissa adder 269, and the shifter 271.
(1) Pre-Processing Start Step
The multiplicand and the multiplier of the single precision are expanded into the double precision and are accommodated respectively into the multiplicand register 251 and the multiplier register 252. At this time, the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e are both converted into the biased expression of the double precision (real exponent value=exponent value -1023.sub.(10)), with 0 being filled in the lower 29 bits of the multiplicand register mantissa portion 251f and the multiplier register mantissa portion 252f. The latch 273 is cleared to 0. Here, the subscript (10) denotes that the decimal number expression is used.
(2) Step 1
By operation of the selector 255 and the selector 256, the exponents of the multiplicand and the multiplier are inputted from the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e into the exponent adder 254 where they are added to accommodate the addition result into the latch 257. The multiplicand upper, lower selecting circuit 260 reads and outputs the upper 27 bits of the multiplicand register mantissa portion 251f (all the effective bits of the mantissa portion of the multiplicand are included therein), and the multiplier upper, lower selecting circuit 261 reads and outputs the upper 27 bits of the multiplier register mantissa portion 252f (all the effective bits of the mantissa portion of the multiplier are included therein). The multiplier 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively into the latch 263 and the latch 264. At the same time, in the sign generating circuit 253, the signs of the multiplicand and the multiplier are read from the multiplicand register sign portion 251 s and the multiplier register sign portion 252s so as to take the exclusive OR of both, and to generate the sign of the product so as to be accommodated in the product register sign portion 724s.
(3) Step 2
As the value retained by the latch 257 is the sum of the biased exponents of the multiplicand and the multiplier, the biasing is double applied. Therefore, -1023 (actually the 2's complement expression is used) from the bias correction value generating circuit 258 is outputted. By operation of the selector 255 and the selector 256, the value of the latch 257 and the output of the bias correction value generating circuit 258 are added in the exponent adder 254 and accommodated again into the latch 257. The product generating adder 265 adds the sum output and the carry output-of the multiplying unit 262 respectively retained in the latch 263 and the latch 264 to accommodate the addition result into the latch 266.
(4) Step 3
The mantissa adder 269 adds the value retained in the latch 266 and output by selector 268 and the value 0 of the latch 273. When overflow from the product generating adder 265 exists at the step 2, namely, when the product of the mantissa is 2 or more, the shifter 271 shifts (at this time, 1 is buried at the most significant bit), in the 1 bit least significant bit direction, the output from the mantissa adder 269 for normalization so as to accommodate the result into the latch 273. By operation of the selector 255 and the selector 256, the exponent adder 254 adds the value of the latch 257 and the constant 1 output by the normalized correction value generating circuit 259 so as to be accommodated again into the latch 257. When overflow from the product generating adder 265 at the step 2 does not exist, namely, when the product of-the mantissa portion is or more and less than 2, the shifter 271 accommodate it as is into the latch 273 without shifting of the output from the mantissa adder 269, since normalization is not required. By operation of the selector 255 and the selector 256, the exponent adder 254 outputs the value of the latch 257 as is and accommodates it again into the latch 257. The sticky bit generating circuit 272 takes the logical OR of the lower 30 bits of the output of the mantissa adder 269 that the sticky bit is 1 if a bit having the value 1 exists in the 30 bits, and the sticky bit is 0 if all 30 bits are 0.
(5) Step 4
The round addition value generating circuit 267 decides whether the round addition is necessary in accordance with the rounding mode, the value of the 25th bit from the most significant bit which is a round bit of the value retained in the latch 273, the sign of the product output by the sign generating circuit 253 (necessary when the round mode is a round toward plus mode and a round toward minus mode) and the value of the sticky bit by the sticky bit circuit 272. The circuit 267 outputs the round addition value D shown in FIG. 26 when the round addition is necessary, and outputs 0 when the round addition is not necessary. By operation of the selector 268, the mantissa adder 269 adds the round addition value output by the round addition value generating circuit 267 and a value retained in the latch 273. At this time, when overflow is caused in the mantissa adder 269, namely, the mantissa is 2 or more by rounding up, the shifter 271 shifts by 1 bit in the least significant bit direction the output from the mantissa adder 269 again for normalization (at this time, 1 is buried at the most significant bit). By operation of the selector 255 and the selector 256, the exponent adder 254 adds the value of the latch 257 and the constant 1 output by the normalized correction value generating circuit 259. When the overflow is not caused in the mantissa adder 269, namely, the mantissa value is 1 or more and less than 2, the shifter 271 outputs the output, as is, from the mantissa adder 269 without shifting since it is not necessary to effect normalization. By operation of the selector 255 and the selector 256, the exponent adder 254 also outputs the value, as is, of the latch 257. In any case, the output of the exponent adder 254 is accommodated into the product register exponent portion 274e, the lower 29 bits of the 53 bits except for the least significant bit of the output of the shifter 271 are masked into 0, are accommodated in the product register mantissa portion 274f so as to complete the processing.
A case where the multiplicand and the multiplier are the double precision, and where the product is also rounded in the double precision, will be described with reference to the operation flow chart of the double precision multiplication shown in FIG. 28. FIG. 28 shows the contents of the operations of each processing step of the exponent adder 254, the multiplying unit 262, the product generating adder 265, the mantissa adder 269, and the shifter 271.
(1) Pre-Processing Start Step
The multiplicand and the multiplier in double precision are respectively accommodated in the multiplicand register 251 and the multiplier register 252. At this time, the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e are both converted into the biased expression of the double precision (real exponent value =exponent value -1023.sub.(10)). The latch 273 is cleared to 0.
(2) Step 1
By operation of the selector 255 and the selector 256, the exponents of the multiplicand and the multiplier are inputted from the multiplicand register exponent portion 251e and the multiplier register exponent portion 252e into the exponent adder 254 where they are added so as to accommodate the addition result into the latch 257. The multiplicand upper, lower selecting circuit 260 reads and outputs the lower 27 bits (the most significant bit is 0) of the multiplicand register mantissa portion 251f, and the multiplier upper, lower selecting circuit 261 reads and outputs the lower 27 bits (the most significant bit is 0) of the multiplier register mantissa portion 252f. The multiplying unit 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively into the latch 263 and the latch 264. At the same time, in the sign generating circuit 253, the signs of the multiplicand and the multiplier are read from the multiplicand register sign portion 251s and the multiplier register sign portion 252s to take the exclusive OR of both, and to generate the sign of the product so as to be accommodated to the product register sign portion 724s.
(3) Step 2
As the value retained by the latch 257 is the sum of the biased exponents of the multiplicand and the multiplier, the biasing is doubly applied. Therefore, -1023 (actually 2's complement expression is used) in outputted from the bias correction value generating circuit 258. By operation of the selector 255 and the selector 256, the value of the latch 257 and the output of the bias correction value generating circuit 258 in the exponent adder 254 are added and are accommodated again into the latch 257. The product generating adder 265 adds the sum output and the carry output of the multiplying unit 262 retained in the latch 263 and the latch 264 so as to accommodate the addition result into the latch 266. The value accommodated in the latch 266 is the least significant partial product. At the same time, the multiplicand upper, lower selecting circuit 260 reads and outputs the lower 27 bits (the most significant bit is 0) of the multiplicand register mantissa portion 251f. The multiplier upper, lower selecting circuit 261 reads and outputs the upper 27 bits of the multiplier register mantissa portion 252f. The multiplying unit 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively into the latch 263 and the latch 264.
(4) Step 3
The mantissa adder 269 adds the value retained in the latch 266 and output by the selector 268 and the value 0 of the latch 273. The shifter 271 shifts by 26 bits in the least significant bit direction the data of 55 bits which consists of 54 bits of the addition result in the mantissa adder 269 and 1 bit being added onto the most significant bit side, where the logical OR of the overflow from the product generating adder 265 at the step 2, and the overflow from the mantissa adder 269 at the step 3 was taken in the "OR" gate 270, so as to accommodate the result into the latch 273. The product generating adder 265 adds the sum output and the carry output of the multiplying unit 262 retained in the latch 263 and the latch 264 so as to accommodate the addition result. The value accommodated in the latch 266 is a first intermediate partial product. At the same time, the multiplicand upper, lower selecting circuit 260 reads and outputs the upper 27 bits of the multiplicand register mantissa portion 252f, and the multiplier upper, lower selecting circuit 261 reads and outputs the lower 27 bits (the most significant bit is 0) of the multiplier register mantissa portion 252f. The multiplying unit 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively into the latch 263 and the latch 264.
(5) Step 4
The mantissa adder 269 adds the value retained in the latch 266 and output by the selector 268 and the output of the shifter 271 retained in the latch 273. The shifter 271 outputs, without shifting, 54 bits of the addition result, as is, in the mantissa adder 269 so as to be accommodated in the latch 273. The product generating adder 265 adds the sum output of the multiplying unit 262 retained in the latch 263 and the latch 264, and the carry output so as to accommodate the addition result. The value accommodated in the latch 266 is a second intermediate partial product. At the same time, the multiplicand upper, lower selecting circuit 260 reads and outputs the upper 27 bits of the multiplicand register mantissa portion 251f, and the multiplier upper, lower selecting circuit 261 reads and outputs the upper 27 bits-of the multiplier register mantissa portion 252f. The multiplying unit 262 executes the multiplication in accordance with the inputs from the multiplicand upper, lower selecting circuit 260 and the multiplier upper, lower selecting circuit 261 so as to accommodate the sum output and the carry output respectively in the latch 263 and the latch 264.
(6) Step 5
The mantissa adder 269 adds the value retained in the latch 266 and output by the selector 268 and the output of the shifter 271 retained in the latch 273. The shifter 271 shifts by 26 bits in the least significant bit direction the data of 55 bits, which consists of 54 bits of the addition result in the mantissa adder 269 and 1 bit being added onto the most significant bit side, where the logical OR of the overflow from the product generating adder 265 at the step 4 and the overflow from the mantissa adder 269 at the step 5 is taken in the "OR" gate 270, so as to accommodate the result into the latch 273. The product generating adder 265 adds the sum output and carry output of the multiplying unit 262 retained in the latch 263 and the latch 264 so as to accommodate the addition result. The value accommodated in the latch 266 is the most significant partial product.
(7) Step 6
The mantissa adder 269 adds the value retained in the latch 266 and output by the selector 268 and the output of the shift 271 retained in the latch 273. When the logical OR of the overflow from the product generating adder 265 at the step 5 and the overflow from the mantissa adder 269 at the step 6 being taken at the logical OR gate 270 are 1, namely, the product of the mantissa portion is 2 or more, the shifter 271 shifts the output from the mantissa adder 269 (at this time, 1 is buried in the most significant bit) by 1 bit in the least significant bit direction so as to accommodate the result in the latch 273. The exponent adder 254 adds the value of the latch 257 and the constant 1 output by the normalized correction value generating circuit 259 so as to be accommodated again into the latch 257. When the value with the logical OR being taken in the logical OR gate 270 is 0, namely, the product of the mantissa portion is 1 or more and less than 2, the output from the mantissa adder 269 is accommodated as is into the latch 273 without shifting since normalization is not necessary. The exponent adder 254 outputs the value of the latch 257 as is by operation of the selector 255 and the selector 256 so as to be accommodated again into the latch 257. The sticky bit generating circuit 272 takes the logical OR of 52 bits with the shift overflow from the least significant bit of 26 bits in the shifter 271 at the step 3 and the shift overflow from the least significant bit of 26 bits in the shifter 271 at the step 5 being combined in it. The sticky bit output is 1 if a bit having a value 1 exists in the 52 bits, and the sticky bit output is 0 if all 52 bits are 0.
(8) Step 7
The round addition value generating circuit 267 determines whether round addition is necessary in accordance with the rounding mode, the value of the least significant bit which is the round bit of the value retained in the latch 273, the sign of the product output by the sign generating circuit 253 (necessary when the round mode is a round toward plus mode and a round toward minus mode) and the value of the sticky bit output by the sticky bit generating circuit 272. The round addition value E shown in FIG. 26 is output when the round addition is necessary, and 0 is output when the round addition is not necessary. By operation of the selector 268, the mantissa 269 adds the round addition value output by the round addition value generating circuit 267 and the value retained by the latch 273. At this time, when overflow is caused in the mantissa adder 269, namely, the mantissa is 2 or more by the rounding up, the shifter 271 shifts by 1 bit in the least significant bit direction the output from the mantissa adder 269 again for normalization (at this time, 1 is buried at the most significant bit). By operation of the selector 255 and the selector 256, the exponent adder 254 adds the value of the latch 257 and the constant 1 output by the normalized correction-value generating circuit 259. When overflow is not caused in the mantissa adder 269, name)y, the mantissa is 1 or more and less than 2, the shifter 1 outputs the value, as is, output from the mantissa adder 269 without shifting, since it is not necessary to effect the normalization. By operation of the selector 255 and the selector 256, the exponent adder 254 also outputs the value, as is, of the latch 257. In any case, the output of the exponent adder 254 is accommodated into the product register exponent portion 274e, and the 53 bits, the output of the shifter 271 except for th least significant bit, are accommodated in the product register mantissa portion 274f so as to complete the processing.
Also, in the conventional floating point data division apparatus, the value of the exponent portion of the divisor is first subtracted from the value of the exponent portion of the dividend so as to obtain the exponent portion of a quotient. As the subtraction values are the difference between the biased exponents, the bias is offset. Therefore, the bias value is added to the subtraction value so as to generate the exponent portion of the quotient correctly biased.
However, in the conventional floating point data addition and subtraction apparatus, the position of the least significant bit (L) for adding the round addition value is fixed for the first time after normalization shift by the barrel shifter 157, and not fixed with respect to the input and output in the adder 154, thus normally resulting in the processing flow of addition or subtraction, normalization, and rounding. Therefore, the addition and subtraction of two mantissas and the addition of the round addition value are required to be respectively effected independently. At least four processing steps in number including the alignment are required as shown in FIG. 8 (a). Also, as the addition or subtraction of the former are effected by the adder 154, and the addition of the latter is effected by the adder 160, two adders are required which presents a problem With respect to increasing the amount of necessary hardware.
In the conventional floating point data multiplication apparatus, the addition of the sum and the carry from the multiplying unit 262, the addition for accumulating the partial products, and the addition of the round addition values are respectively effected independently, and four processing steps are required in the case of the single precision multiplication, and seven processing steps are required in the case of the double precision multiplication. Also, the addition of one former is effected with the product generating adder 265, and the addition of the latter two are effected by the mantissa adder 269, thus requiring two adders, which is a problem in that an increased amount of hardware is needed.
Also, in the conventional floating point data division apparatus, the subtraction value for simply subtracting the exponent portion of the dividend and the exponent portion of the divisor is offset in bias, and a later step for correcting the bias becomes necessary, which presents a problem in that the hardware is required for effecting the bias correction.